Quadrature Oscillator-2 (IC and PCB layout)

In this section, I will mention what I did after the theory section. UMC 180 nm was used to make this integrate circuit. Figure 1. is the topology of Quadrature Oscillator and Table.1 is its dimension. 

Figure 1. Topology of Quadrature Oscillator

R1	5k W
R2	2k W
R3	2k W
R4	5k W
R	816W
2R	1.632kW
Rf	1.59kW
C1	19.5nF
C2	19.5nF

Table. 1 Dimension of Quadrature Oscillator

Figure 2. is the layout of this chip. The chip size: 505.32μm*546.690μm, 40 transistors, power dissipation: 32.2182 mW, and MAX. Frequency: 20k Hz. This chip confirm DRC and LVS rules. Here I use guard ring to protect the signal and bypass capacitor to decrease the noise. However, in Figure. 2, we can find the width trace is very small, in this situation, the resistance of trace will increase, and easily influence the signal. 

Figure 2. Layout of Quadrature Oscillator.

 Figure 3, 4 are PCB design and its layout. 

Figure 3. PCB design

Figure 4. PCB Layout

The tables below are prediction and real test results. The result is partial work, because the frequency is only 6k Hz. Here is the comments of this project.

First, redesign the topology of operating amplifier and increase its current. 

Second, change the layout position.

Third, increase the width of trace and via in layout. 

Fourth, in this project, the capacitor is unchangeable, use different size of capacitor may be a way to increase the frequency. 

Predict dimension :

Specification	Post-layout imulation
Power supply	+-0.9V
Total current	17.899mA
Power dissipation	32.2182mW
Oscillator Frequency	20kHz
Chip size	544μm*505μm

 Real dimension:

Specification	Post-layout simulation
Power supply	+-1.0V
Total current	6mA
Power dissipation	6mW
Oscillator Frequency	6.124kHz
Chip siz	544μm*505μm

Figure 5. Testing situation