Standard Digital CMOS Design-1

Standard Cell

This project would involve some standard cells of cmos digital circuit. Some basic logic circuit can be made by using these standard cells.

1.1 Inverter

Inverter is a very basic stand cell, which output is opposite of input voltage. Fig. 1.1 is the symbol of inverter. In this symbol, the vdd is voltage supply, gnd is ground, vin is input voltage, and vout is the output voltage.

Figure 1.1 Symbol of Inverter

Fig 1.2 is the cmos digital circuit of inverter, because the transmit speed of Pmos is faster than Nmos, so the width of Pmos should be 2 to 3 times bigger than width of Nmos. In Fig. 2, the width of Pmos is 320 nm, and the Nmos is 160 nm. In this library, there is a “subc” parameter which is essential in every Nmos, which can help the base of Nmos connect to the ground.

Figure 1.2 CMOS circuit of Inverter

Fig 1.3 is Noise of inverter, the noise is obviously in low frequency, the reason is the size of cmos gate is very small, therefore, the leak voltage and current is more than bigger size of cmos. In the low frequency, this phenomenon is more obviously. 

Figure 1.3 Noise Response of Inverter

Fig 1.4 shows the testing of inverter. In this testing, the voltage supply is 1 V and it’s enough to drive this circuit. Moreover, the vpulse is added in this circuit. 

Figure 1.4 Testing of Inverter

Figure 1.5 Simulation and Power consumption of Inverter

Fig 1.5 is the simulation and power of inverter, In the simulation, the output voltage is opposite compare with the input voltage. Besides, the power consumption is very small, only Nano watt. The power consumption would increase only when the status change.

This section, I will involve the delay time. In the schematic, the delay is 5.001E-6. The reaction time is very quick and good enough to show very precisely data. 

1.2 NAND

Nand is a very common logic gate. It can be used in full adder, multiplier and divider. Fig. 1.6 is the symbol of Nand, which is combined with a vdd, gnd, two input and one output. 

Figure 1.6 Symbol of NAND

Fig 1.7 is cmos circuit of Nand, which is combined with two parallel Pmos and two series Nmos. Moreover, the size of Pmos is two times than Nmos. When the a, b is 1 V, the output voltage is 0 V. Nmos of a b are combined by series, while the a b of Nmos connect, vout will equal to gnd.

Figure 1.7 CMOS circuit of NAND

Fig. 1.8 is output voltage of noise. If the frequency increase, the noise will be smaller.

Figure 1.8 Noise of NAND

Fig. 1.9 is the testing of Nand, a and b are connected to different vpulse to calculate the truth table.

Fig. 1.10 is the testing of Nand. The voltage supply is 1 V.

Figure 1.9 Testing of NAND

Fig. 1.10 is the simulation and power consumption of Nand. When the a and b equal to power supply, v output voltage will equal to gnd. Every time the clock change, the power consumption will increase, but still less than 5 uW. And the delay is 7.501E-6

Figure 1.10 Simulation and Power consumption of NAND

1.3 NOR 

Fig. 1.11 is the symbol of Nor, there are two input, which are a and b, voltage supply, ground and one output voltage.

Figure 1.11 Symbol of NOR

Fig. 1.12 is the cmos circuit of Nor. When a and b are ‘0’, output voltage will equal to “1”. In other situation, the output equals to “0”.

Figure 1.12 CMOS circuit of NOR

Fig. 1.13 is the output noise of nor. While the frequency increase, the noise will become smaller. The reason is these MOSFETs are very small and usually work on high frequency. 

Figure 1.13 Noise of NOR

Fig. 1.14 is the simulation and power of Nor. In the simulation, if the a and b is “0”, the output voltage will be “1”. If each one of a or b is “1” the output voltage is “0’. And the delay 238.4E-12

Figure 1.14 Simulation and Power consumption of NOR

1.4 AND

Fig. 15 is the cmos circuit of and gate. It’s a nand gate and inverter. While the a and b are “1”,

the output voltage is “0” and through to inverter become a “1”.

Figure 1.15 Symbol of AND

Fig. 1.17 is the output noise of and gate. While the frequency increase, the noise will become smaller.

However, because this gate is based on nand gate and inverter, the noise will bigger than nand gate.

Figure 1.16 CMOS circuit of AND

Figure 1.17 Noise of AND

Fig. 1.18 is the simulation and power consumption of and, while the status change, the power 

consumption will increase and then go back to normal status. Delay time is 2.501E-6

Figure 1.18 Simulation of Power Consumption of AND

1.5 OR

Fig. 1.19 is the symbol of or gate. Or gate means if each a or b are “1”, the output voltage will be “1”.

Figure 1.18 Symbol of OR

Fig. 1.20 shows the circuit of or gate. It combines an nor and a inverter together. Fig. 1.20 shows the

output noise of or gate. While the frequency increase, the noise will become smaller.

Figure 1.20 Logic gate of OR

Figure 1.21 Noise of OR

Fig 1.22 is the simulation and power of or gate. The a and b are input voltage, only when the a and b are “0”, the output voltage would be 0, then. The power consumption is very small, only 1.2 uW. Delay time is 7.502E-6

Figure 1.22 Simulation and Power consumption of OR

1.6 XOR

Fig. 1.23 are the symbol or Xor. It combines three logic gates; therefore, the delay may increase and also the noise and power consumption. However, it often be used in the current technology to the full adder or multiplier.

Figure 1.23 Symbol of XOR

Fig. 1.24 shows the cmos logic circuit of Xor. There are one nand gate, or gate and and gate. While each a or b are “1”, the output voltage will be “1”. On the other hand if both a and b are “0” or “1” the output voltage will be “0”.

Figure 1.24 Logic gate of XOR

Fig. 1.25 is the noise of xor gate. The noise is a little bigger than the previous cells, because there are three different gates, but still shows a good performance. 

Figure 1.25 Noise of XOR

Fig. 1.26 is the simulation of xor gate. While the a and b are “0” or “1”, the output voltage will be “0”. On the other hand, if each a or b are “1”, the output voltage will be “1”. Delay time is 2.5E-6.

Figure 1.26 Simulation and Power consumption of XOR

1.7 XNOR

Fig. 1.27 is the symbol of xnor gate. It very similar with xor gate. However the and gate is replaced by nand gate.

Figure 1.27 Symbol of XNOR

Fig. 1.28 is the cmos logic gate of xnor gate. There are a or gate, and two nand gates.

Figure 1.28 Logic gate of XNOR

Fig. 1.29 is the noise of XNOR gate. While the frequency increases, the noise will become smaller. 

Figure 1.29 Noise of XNOR

Fig. 1.30 is the simulation and power consumption of Xnor gate. While both a and b are “0” or “1”, the output voltage will be “1”. On the other hand, while each a or b are “0” or “1”, the output signal is “0”. Delay time is 5.001E-6

Figure 1.30 Simulation and Power Consumption of XNOR

2.1 FULL ADDER

Figure 1.31 Truth Table of Full Adder

Fig. 1.32 is the symbol of Full adder. Full adder usually be used in many different ways. It can be combined with two half adder or cmos logic gate. C is carry in, and a, b are input signal. While two or three of a, b, and c are “1”, the carry out will be one and push the input signal to next carry in. While one or three of a, b, and c are “1”, the So will be “1”. In others situation, the So will be “0”.

Figure 1.32 Symbol of Full Adder

Fig. 1.33 are the cmos logic circuit of Full adder. I use two half adder and one or gate to complete the circuit. Therefore, there are five logic gates. Three input signal and two output signals, carry out and sum. 

Figure 1.33 Logic Gate of Full Adder

Fig. 1.34 is the noise of Full adder; the noise is as small as other circuit. In the previous, I tried to use MOSFETs instead of logic gate to build this circuit, the noise and signal is not very well. Therefore, I changed back to the logic gate. 

Figure 1.34 Noise of Full Adder

Fig. 1.35 is the simulation and power consumption of Full adder. While two or three of a, b, and c are “1”, the carry out will be one and push the input signal to next carry in. While one or three of a, b, and c are “1”, the So will be “1”. In others situation, the So will be “0”. In this circuit, the power consumption is higher than previous design, but still very good devices. Delay time is 668.7E-12.

Figure 1.35 Simulation and Power Consumption of Full Adder

2.2 4-1 Multiplexer

Fig. 1.36 is the symbol of 4-1 multiplexer. When the s0 and s1 changed they can determine the output voltage will equal to a, b, c, or d. It can be control be use a very simple switch.

Figure 1.36 Symbol of 4-1 Multiplexer

Fig. 1.37 is the cmos circuit of 4-1 multiplexer. In the design, I just let s0 and s1 as input signal as 

other input signal. In this circuit, I use eight different switch to control the signal and output.

Figure 1.37 Logic gate of 4-1 Multiplexer

Because this circuit doesn’t use complicate design, therefore, the noise is small. As usual, the noise decrease when the frequency increase.

Figure 1.38 Noise of 4-1 Multiplexer

Fig. 1.39 is the simulation and power consumption of testing. This graph may looks a little complicated, but it’s confirm with our target. Delay time is 6.501E-6.

Figure 1.39 Simulation and Power Consumption of 4-1 Multiplexer

2.3 D Flip Flop

Fig 1.40 is a d flip flop. D flip flop is a basic register, with usually be used in the electronic devices. Which can storage the data by clock.

Figure 1.40 Symbol of D Flip Flop

Fig. 1.41 is the logic circuit of D flip flop. It combines two nand, two nor, and one inverter. In this circuit, when the Q is “0”, the Q_bar will be “1”. And input signal D equal to Q.

Figure 1.41 Logic Gate of D Flip Flop

Fig. 1.42 is the output noise of D Flip Flop. 

Figure 1.42 Noise of D Flip Flop

Fig 1.43 is the simulation and power consumption of D flip flop. A is clock and b is input D. Every time when the clock rise, the status will change based on the input voltage D. Therefore, by changing the clock frequency, we can easily storage the data and control other devices. Delay time is 35.37E-12.

Figure 1.43 Simulation and Power Consumption of D Flip Flop

Conclusion

This is the tutorial what I made for Digital IC circuit while I was doing teaching assistant. In this tutorial, we introduce some basic but useful logic gates. Next, we will talk about some higher level logic gate and its applications. 

Thank you, 

Shang-kai, Wei.